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| RDA012M4MS DATASHEET DS_0017PB0-2805 RDA012M4MS 12 Bit 1.3 GS/s Master-Slave 4:1 MUXDAC Features 12 Bit Resolution 1.3 GS/s Sampling Rate 4:1 Input Multiplexer Master-Slave Operation for Synchronous Operation of Multiple Devices Differential Analog Output Input Code Format: Offset Binary Output Swing: 600 mV with 50 Termination 3.3V NMOS-Compatible Data Inputs Differential ECL or Sinusoidal Clock Input LVDS Compatible Clock Output 10 Bit Static Linearity Reference Output/Input Pin for Accurate Full-Scale Adjustment. 3.3V and -5.2V Power Supply 77 Lead HSD Package Figure 1 - Functional Block Diagram Product Description The RDA012M4MS is a digital-to-analog converter (DAC) with a 4:1 input multiplexer and a maximum update rate of 1.3GS/s. The RDA012M4MS features master-slave operation that simplifies synchronization when multiple devices are required, such as in an I-Q modulation scheme. The integrated DAC utilizes a segmented current source to reduce the glitch energy and achieve high linearity performance. For best dynamic performance, the DAC outputs are internally terminated with 50 resistance, and outputs a nominal full-scale current of 12mA when terminated with external 50 resistors. For a convenient interface with most CMOS ICs, the digital data inputs are low voltage NMOS compatible. Ordering information PART NUMBER RDA012M4MS-DI RDA012M4MS-HD EVRDA012M4MS-HD DESCRIPTION 12 BIT 4:1 MUX 1.3GS/s DAC, DIE 12 BIT 4:1 MUX 1.3GS/s DAC, HSD Package RDA012M4MS-HD Evaluation Board Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 1 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Absolute Maximum Ratings Supply Voltages Between GNDs ................................... -0.3V to +0.3V Between VCCs ..................................... -0.3V to +0.3V VCCs to GND .......................................... 0V to +3.8V RF Input Voltages CLKIP, CLKIN to GND ................................. 0V to VCC HS Digital Input Voltages DI<0:11> ......................................................... 0V to VCC Output Termination Voltages DOUTP, DOUTN to GND ..............................0V to VCC Temperature Operating Temperature........................... -30 to +100 C Case Temperature................................. -15 to +85 C Junction Temperature..................................... +120 C Lead, Soldering (10 Seconds) .......................... +220 C Storage................................................ -40 to 125 C Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 2 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Electrical Specification PARAMETER ACCURACY Differential Nonlinearity Integral Nonlinearity DYNAMIC PERFORMANCE Spurious Free Dynamic Range SYMBOL DNL INL CONDITIONS, NOTE TEST LEVEL 2 2 1 1 1 MIN TYP 2 2.5 56 53 50 MAX UNITS LSB LSB dBc dBc dBc dB dB 630 0 1200 12 1260 mVp-p mV mVp-p mA ps ps ps 800 -2.0 55 mVpp V fF MHz MHz mVpp mV MHz MHz mVpp mV MHz MHz V V ps ps SFDR1 Fclk = 800MHz , Fout = 267MHz SFDR2 Fclk = 1000MHz , Fout = 333MHz SFDR3 Fclk = 1300MHz , Fout = 400MHz Signal Noise Ratio SNDR Clock Feedthrough FD ANALOG SIGNAL OUTPUT (OUTP, OUTN) Single Ended, 50 Termination to Full-scale Output Range VFSS Ground Single Ended, 50 Termination to Full-scale Output Range VFSRS Ground (MIN=000h, MAX=FFFh) Differential with 50 Termination to Full-scale output swing VFSD Ground on each output Output current IOUT Rise Time TR,OUT 20%-80% with FSR output Fall Time TF,OUT 20%-80% with FSR output Settling Time TSETTL CORE CLOCK INPUT (HCLKIP, HCLKIN) Amplitude VCPP,HCLKI Differential ECL Common Mode Voltage VCM,HCLKI Input Resistance RHCLKI Input Capacitance CHCLKI Maximum Frequency FMAX,HCLKI Minimum Frequency FMIN,HCLKI CLOCK INPUT (LCLKIP, LCLKIN) Amplitude VCPP,LCLKI Differential LVDS Common Mode Voltage VCM,LCLKI Input Resistance RLCLKI Maximum Frequency FMAX,LCLKI Minimum Frequency FMIN,LCLKI CLOCK OUPUT (LCLKOP, LCLKON) Amplitude VCPP,LCLKO Common Mode Voltage VCM,LCLKO Maximum Frequency FMAX,LCLKO Minimum Frequency FMIN,LCLKO DIGITAL INPUTS (A<0:11>, B<0:11>, C<0:11>, D<0:11>) Input High Voltage VIH Input Low Voltage VIL Input Resistance RDIN Setup Time tST,DTHCK From data input to LCLKO Hold Time tHL,DTHCK From LCLKO to data input 2 570 -650 600 2 3 1140 1 1 3 3 3 2 2 3 3 3 2 2 3 3 2 2 3 3 400 -0.8 45 1300 600 -1.5 50 1 250 0.9 325 0.25 250 0.9 325 350 1.2 450 1.5 0.25 0.9 -0.4 300 -50 VCC 0.4 350 1.2 100 450 1.5 Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 3 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Electrical Specification PARAMETER SYMBOL CONDITIONS, NOTE TEST LEVEL MIN TYP -2.0 Internally generated Internally generated For externally driven VREFA, VREFD 3 3 3 -1.9 -1.9 500 3.1 -5.4 -5.4 Total dissipation Positive supply Negative supply, analog Negative supply, digital -2.0 -2.0 560 3.3 -5.2 -5.2 3300 500 500 2300 -2.1 -2.1 620 3.5 -5.0 -5.0 MAX UNITS V V V V V V mW mW mW mW C C TERMINATION (VTT) HCLKI Termination VTT Voltage REFERENCE (VREFA, VREFD) Analog Reference VREFA Digital Reference VREFD Input Resistance RVREF POWER SUPPLY Positive Supply VCC Negative Supply, Analog VEEA Negative Supply, Digital VEED Power Dissipation P Power Dissipation PVCC Power Dissipation PVEEA Power Dissipation PVEED OPERATING RANGE Ambient Temperature TA Junction Temperature TJ 120 Test Levels TEST LEVEL 1 2 3 1 TEST PROCEDURE 1,2 100% production tested at TA = 25C 1 Sample tested at TA = 25C unless other temperature is specified Guaranteed by design and/or characterization testing All tests are continuous, not pulsed. Therefore, Tj (junction temperature) > Tc (case temperature) > Ta (ambient temperature). This is the normal operating condition and is more stressful than a pulsed test condition. The tests are conducted with the power set to VCCMIN and to VCCMAX. 2 Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 4 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Pin Description P/I/O P P P P I I I I I I I I I I I I I I O O PIN 7, 14, 39, 62 68, 71, 72, 73, 74, 75, 76 8, 12, 26, 52, 64, 67 Bottom Plate 77 10 4 6 5 3 24 25 2 1 9, 16, 20, 27, 31, 35, 40, 44, 48, 53, 57, 61 11, 17, 21, 28, 32, 36, 41, 45, 49, 54, 58, 63 13, 18, 22, 29, 33, 37, 42, 46, 50, 55, 59, 65 15, 19, 23, 30, 34, 38, 43, 47, 51, 56, 60, 66 70 69 NUM. 4 7 6 1 1 1 1 1 1 1 1 1 1 12 12 12 12 1 1 NAME VCC VEEA VEED GND VREFA VREFD VTT MSM HCLKIP HCLKIN LCLKIP LCLKIN LCLKOP LCLKON DIA<0:11> DIB<0:11> DIC<0:11> DID<0:11> OUTP OUTN FUNCTION +3.3V Digital Power Supply -5.2V Analog Power Supply -5.2V Digital Power Supply Ground -2V Reference Voltage Digital Circuitry Bias Reference. Bypass to Ground HCLKI Clock Termination Voltage Master-Slave Mode Selection: Float - Master GND - Slave Clock Input Low Clock Input Low Clock Output DIA Is Channel A Digital Bit i Input. MSB is bit 11 DIB Is Channel B Digital Bit i Input. MSB is bit 11 DIC Is Channel C Digital Bit i Input. MSB is bit 11 DID Is Channel D Digital Bit i Input. MSB is bit 11 Differential Output Pin Layout (TOP view) Figure 2 - RDA012M4MS-HD pinout (top view). Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 5 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Pad Layout Figure 3 - RDA012M4MS pad layout. Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 6 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Theory of Operation For best dynamic and static performance, the DAC employs 6-bit segmentation. The 3.3V NMOS compatible 12-bit digital data inputs are latched by a master-slave flip-flop immediately after the input buffer to reduce the data skew. The four-channel data are combined together by the 48:12 MUX and latched again. The 6 MSB data bits are decoded into thermometer code by a two-stage decoding block, and the 6 LSB data bits are transported through the delay equalizer block. The digital data are synchronized again by a second master slave flip-flop to reduce the switching glitch. The decoded 6 MSB data drive 63 identical current switches, and the 6 LSB data drive 6 current switches. The output nodes from the LSB current switches are connected to the analog output through an R-2R ladder to generate the binary output. The DAC output full-scale voltage follows the relationship VFS = 0.3xVREF. An internal reference circuit with approximately -10dB supply rejection is integrated on chip for application convenience. The reference pin is provided for monitoring and for bypass purposes. To band-limit the noise on the reference voltage, the reference pin should be bypassed to the GNDA node with capacitance > 100pF. The VREF pin can also be used to override the internal reference with an accurate, temperature-compensated reference. external voltage The timing diagram is shown in figure 3. The 1.3GHz external clock (HCLK) is divided by 2 and 4 resulting in the MUX internal selection signals S0 and S1. A low-speed clock (LCLK) is provided to drive the external digital. The fourchannel data input are latched with an internal clock that is synchronized with the LCLK. Controlled by S0 and S1, input data are fed to the 1.3GS/s DAC in the order shown. For applications requiring two MUXDACs, such as quadrature modulation, the RDA012M4MS offers master and slave mode operation. This provides synchronization between the two MUXDACs in a straightforward manner. Figure 4 illustrates two MUXDACs in an I-Q configuration and 1 GS/s conversion rate. The I-MUXDAC is in master mode and the Q-MUXDAC is in slave mode. The master MUXDAC generates an LVDS compatible 250MHz clock signal that is input to the slave MUXDAC were it is used to synchronize the generation of the select signal for the input muxes. The slave device then feeds this clock to the FPGA clock driver. For proper synchronization, the delay associated with the LVDS clock signal from master to slave MUXDAC must not exceed one clock period of the high-speed clock. Figure 4 - Input Timing Diagram. Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 7 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Signal Description HIGH SPEED INPUT CLOCK. The RDA012M4MS high-speed clock input is differential and can be driven from typical ECL circuits. Also a differential sinusoidal clock can be used. The HCLKIP and HCLKIN inputs, are internally terminated with 50 to VTT which should be connected to a well decoupled -2.0 volt supply. Since the MUXDAC's output phase noise is directly related to the input clock noise and jitter, a low-jitter clock source is ideal. The internal clock driver generates very little added jitter (~100fs). A 500MHz MUXDAC output demands a white noise induced clock jitter of less than 250fs for a 10-bit equivalent, 62dB SNDR. DATA INPUT. The data inputs are 3.3V NMOS-compatible. The data is interleaved according to significant bit. For example, consecutive data pins will occur as A0, B0, C0, D0, A1, B1, etc. OUTPUT CLOCK. Output clock LCLKOP and LCLKON are supplied for the DSP/FPGA/ASIC in slave mode, or connected to another MUXDAC if in master mode. They are LVDS compliant and needs to be terminated with a100 resistor in front of the clock driver for the ASIC/DSP. For application convenience, the data input's setup and hold time is specified with respect to the LCLKO. It should be noted that LCLKOP and LCLKON are driven by the MUXDAC and the waveforms of these signals are better defined at the receiver end; that is, near the ASIC/DSP chip that provides the input data for the MUXDAC. The system designer should consider the delay associated with the signal routing in the system's timing budget. In figure 6, the setup and hold time of the LCLK to data transition are defined at the MUXDAC side. Data transitions of the data input have to occur during the "Valid Data Transition Window." The timing margin seen from the MUXDAC is TP-TS where TP is the LCLKO period and TS is the setup time, assuming that the ASIC chip takes LCLKO as the clock input and its outputs are latched at the falling edge of the clock. From the ASIC/DSP end, however, the timing margin is decreased by the amount equal to the sum of the data delay and clock delay between the two chips, as noted in the lower part of the diagram. ANALOG OUTPUT. The outputs DACOUTP and DACOUTN should both be connected though a 50 resistor to ground. This will give a full-scale amplitude of 0.6 volt (both outputs must be terminated), 1.2 volt differentially. The output common mode can be changed by terminating the load resistors to a different voltage. The device is optimized to perform best when connected to a voltage between 0 and 1 volt, however. For reliable operation, the output termination voltage should not exceed 3 volts. REFERENCE. VREFA is provided for added control of the fullscale amplitude output. The internal reference circuit is designed to provide -2.0 volts, which can change up to 5% as the supply voltage and/or operating temperature changes. If the user prefers accurate absolute full-scale, use an external voltage reference with low output impedance to override the internal reference. The output full-scale voltage follows the relationship VFS = 0.3xVREF. Note that the MUXDAC is optimized to have the best performance with a reference voltage of -2.0 volts. The output resistance of the reference node is 560 10%. VREFD allows adjusting of the digital circuitry bias point for varying input voltage swings. In most cases, VREFD should be bypassed to GND. Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 8 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Typical Operating Circuit Figure 5 - RDA012M4MS typical operating circuit using the internal voltage reference. Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 9 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Figure 6 - RDA012M4MS typical operating circuit in master-slave mode using external voltage reference. Figure 7 - RDA012M4MS recommended placement in master-slave mode to minimize LCLK routing. Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 10 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Typical Performance 0 -10 -20 -30 Signal (dB) -40 -50 -60 -70 -80 -90 0 50 100 150 200 Fclk (MHz) 250 300 350 400 Figure 8 - Output spectrum at Fclk=800MHz, Fout=270MHz 0 -10 -20 -30 Signal (dB) -40 -50 -60 -70 -80 -90 0 100 200 Fclk (MHz) 300 400 500 Figure 9 - Output spectrum at Fclk=1000MHz, Fout=340MHz 0 -10 -20 -30 Signal (dB) -40 -50 -60 -70 -80 -90 0 100 200 300 Fclk (MHz) 400 500 600 Figure 10 - Output spectrum at Fclk=1300MHz, Fout=340MHz Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 11 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Package Information The package is a 77 pin HSD with a heat sink slug on the package's bottom. The leads are gull-winged formed and trimmed to 0.053 inch (1.35 mm) in lenght. Figure 11 - RDA012M4MS-HD package, dimensions shown in inches (mm). Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 12 of 13 RDA012M4MS DATASHEET DS_0017PB0-2805 Figure 12 - RDA012M4MS-HD footprint, dimensions shown in inches (mm). Rockwell Scientific reserves the right to make changes to its product specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use. Page 13 of 13 |
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